1. Field of the Invention
The present invention relates to a shift register, and more particularly, to a shift register for use as a scanning-line driving circuit for an image display apparatus or the like, which is formed of field effect transistors of the same conductivity type only.
2. Description of the Background Art
An image display apparatus (hereinafter referred to as a “display apparatus”) such as a liquid crystal display includes a display panel in which a plurality of pixels are arrayed in a matrix. A gate line (scanning line) is provided for each row of pixels (pixel line), and gate lines are sequentially selected and driven in a cycle of one horizontal period of a display signal, so that a displayed image is updated. As a gate-line driving circuit (scanning-line driving circuit) for sequentially selecting and driving pixel lines, i.e., gate lines, a shift register for performing a shift operation in one frame period of a display signal can be used.
To reduce the number of steps in the manufacturing process of a display apparatus, such shift register used as the gate-line driving circuit is preferably formed of field effect transistors of the same conductivity type only. Accordingly, various types of shift registers formed of N- or P-type field effect transistors only and display apparatuses containing such shift registers have been proposed (e.g., Japanese Patent Application Laid-Open Nos. 2004-246358 and 2001-350438). As a field effect transistor, a metal oxide semiconductor (MOS) transistor, a thin film transistor (TFT), or the like is used.
A typical shift register shown in, e.g., FIG. 1 of JP2004-246358 includes, in the output stage, a first transistor (pull-up MOS transistor Q1) connected between an output terminal (first gate-voltage signal terminal GOUT in JP2004-246358) and a clock terminal (first power clock CKV) and a second transistor (pull-down MOS transistor Q2) connected between the output terminal and a reference voltage terminal (gate-off voltage terminal VOFF). The shift register also includes an inverter (transistors Q6, Q7) for inverting the potential of the gate of the first transistor and outputting the inverted potential to the gate of the second transistor.
In such shift register, a clock signal input to the clock terminal with the first transistor turned on and the second transistor turned off by a predetermined input signal (an output signal GOUT[N-1] of the previous stage) is transmitted to the output terminal, so that an output signal is output. In contrast, the first transistor is turned off and the second transistor is turned on during a period in which the input signal is not input, so that the clock signal is not transmitted to the output terminal.
A field effect transistor such as TFT has a gate-to-drain overlap capacitance between the gate and drain (hereinafter briefly called “an overlap capacitance”). Accordingly, the gate of the first transistor may rise in potential through a coupling induced by the overlap capacitance on the rising edge of a clock signal input to the drain, even when the first transistor is off. When the gate of the first transistor rises in potential, the gate of the second transistor drops in potential by the action of inverters. This in result reduces the resistance of the first transistor and increases the resistance of the second transistor. This in turn increases the output terminal in potential, which may cause a malfunction of unnecessary activation of a gate line connected thereto.
A display apparatus employing amorphous silicon TFTs (a-Si TFTs) as shift registers of a gate-line driving circuit easily achieves large-area display with great productivity, and is widely used as the screen of a notebook PC, a large-screen display apparatus. etc.
Conversely, an a-Si TFT tends to have its threshold voltage shifted in the forward direction when the gate electrode is continuously forward-biased (dc-biased), resulting in degraded driving capability. Particularly in a shift register of a gate-line driving circuit, the gate of the second transistor is continuously forward-biased for as long as one frame period (about 16 ms), which degrades the second transistor in driving capability, whereby the aforementioned malfunction is likely to occur (which will be described later in detail).